/*
 * @Author: Laputa
 * @Version: V0.0
 * @Date: 2023-10-08 10:10:27
 * @LastEditors: Laputa
 * @LastEditTime: 2023-12-27 13:55:28
 * @Description: This file provides firmware functions to manage the following
 *              functionalities of the CLOCK part.
 *
 *              Get System Clock
 *              Chip PLL Initialization
 *              Chip Clock Output Control
 *              Chip Sleep Initialization
 *              ADC Module Clock Control
 *              WatchDog Module Clock Select
 *              Module Clock Stop Control
 *              Clock Masuerer usage
 *
 *
 * Copyright (c) 2023 by Levetop, All Rights Reserved.
 */

#include "lt168_clock.h"

uint32_t SYS_CLOCK = 168000000;
uint32_t OSC = 12000000;//外部时钟

/*******************************************************************************
 * Code
 ******************************************************************************/


void Clock_Init(UINT32 sys_clk_mhz)
{
	uint32_t tempReg = 0;
	PLL_Set_parameter pll;

	//PLL = XIN*M/N/NO;
	//Fout = PLL/DIV;
	if(sys_clk_mhz>200) sys_clk_mhz = 200;

	pll.OD = 0; //OD = 1
	if(sys_clk_mhz>=100)
	{
		pll.M = sys_clk_mhz;
		pll.N = 6;
		pll.DIV = 0;			//sys_clk = PLL_OUT/2/OD
	}
	else if(sys_clk_mhz>=50)
	{
		pll.M = sys_clk_mhz*2;
		pll.N = 6;
		pll.DIV = 2;			//sys_clk = PLL_OUT/4/OD
	}
	else if(sys_clk_mhz>=25)
	{
		pll.M = sys_clk_mhz*4;
		pll.N = 6;
		pll.DIV = 4;			//sys_clk = PLL_OUT/8/OD
	}
	else
	{
		pll.M = sys_clk_mhz*8;
		pll.N = 6;
		pll.DIV = 8;			//sys_clk = PLL_OUT/8/OD
	}

	pll.OSC = OSC;

	/* SYNCR */
	CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (0x01<<30); /* 解锁寄存器 */
	CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (0x02<<30); /* 解锁寄存器 */
	CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (0x03<<30); /* 解锁寄存器 */

	Bit_Set(CLOCK->SYNCR, CLOCK_SYNCR_PLLSRCEN_MASK); 	/* PLL没有准备好时，系统时钟使用外部12M */

	Bit_Clear(CLOCK->SYNCR, CLOCK_SYNCR_PLLEN_MASK);  /* Disable PLL */

	/* PLLCSR */

	CLOCK->PLLCSR = (CLOCK->PLLCSR & ~CLOCK_PLLCSR_PLLCSRTEST_MASK) | (0x01 << 30); /* 解锁寄存器 */
	CLOCK->PLLCSR = (CLOCK->PLLCSR & ~CLOCK_PLLCSR_PLLCSRTEST_MASK) | (0x02 << 30);/* 解锁寄存器 */
	CLOCK->PLLCSR = (CLOCK->PLLCSR & ~CLOCK_PLLCSR_PLLCSRTEST_MASK) | (0x03 << 30);/* 解锁寄存器 */

	tempReg = CLOCK->PLLCSR;

	tempReg = CLOCK_PLLCSR_PLLM(pll.M) | CLOCK_PLLCSR_PLLOD(pll.OD) | CLOCK_PLLCSR_PLLN(pll.N);

	CLOCK->PLLCSR = tempReg;


	Bit_Set(CLOCK->SYNCR, CLOCK_SYNCR_PLLEN_MASK);  /* Enable PLL */
	for (;Bit_Read(CLOCK->PLLCSR,CLOCK_PLLCSR_PLLOCK_MASK) == 0;) /* 等待PLL锁定 */
	{
		asm("nop");
	}

	tempReg = CLOCK->SYNCR;

	Bit_Clear(tempReg, CLOCK_SYNCR_PLLDIV_MASK);

	tempReg |= CLOCK_SYNCR_PLLDIV(pll.DIV);

	CLOCK->SYNCR = tempReg;

	asm("nop");
	asm("nop");
	asm("nop");

	Get_SysClock();
}


/**
 * @brief  Get System Clock
 * @return {uint32_t} Current System Clock
 */
uint32_t Get_SysClock(void)
{
    uint8_t OD = 0U;

    /* chip use PLL output as clock source */
    if (Bit_Read(CLOCK->SYNCR, CLOCK_SYNCR_PLLEN_MASK) == CLOCK_SYNCR_PLLEN_MASK &&
        Bit_Read(CLOCK->PLLCSR, CLOCK_PLLCSR_PLLOCK_MASK) == CLOCK_PLLCSR_PLLOCK_MASK) {

        SYS_CLOCK = (LT168_OSC / ((CLOCK->PLLCSR & CLOCK_PLLCSR_PLLN_MASK) >> CLOCK_PLLCSR_PLLN_SHIFT)) * (CLOCK->PLLCSR & CLOCK_PLLCSR_PLLM_MASK);

        switch (((CLOCK->PLLCSR & CLOCK_PLLCSR_PLLOD_MASK) >> CLOCK_PLLCSR_PLLOD_SHIFT)) {
            case 0:
                OD = 1U;
                break;
            case 1:
                OD = 2U;
                break;
            case 2:
                OD = 4U;
                break;
            case 3:
                OD = 8U;
                break;
            default:
                break;
        }

        SYS_CLOCK /= OD;

        if (((CLOCK->SYNCR & CLOCK_SYNCR_PLLDIV_MASK) >> CLOCK_SYNCR_PLLDIV_SHIFT) == 0U)
            SYS_CLOCK /= 2U;
        else
            SYS_CLOCK /= ((CLOCK->SYNCR & CLOCK_SYNCR_PLLDIV_MASK) >> CLOCK_SYNCR_PLLDIV_SHIFT) * 2U;
    }
    /* chip use external_crystal_oscillator(12MHz) as clock source */
    else
        SYS_CLOCK = LT168_OSC;

    return SYS_CLOCK;
}


/**
 * @brief  PLL Initialize
 * @return {ResultStatus} OK/ERROR.
 */
ResultStatus CLOCK_PLL_Init(void)
{
    uint32_t tempReg = 0U;

    /* Check pll parameter */
    if (PLL_N > 15U || PLL_N < 1U)
        return ERROR;
    if (PLL_M > 16383U || PLL_M < 4U)
        return ERROR;
    if (PLL_OD > 3U)
        return ERROR;
    if (PLL_DIV > 63U || PLL_DIV < 0U)
        return ERROR;

    if ((LT168_OSC / PLL_N) > 50000000U || (LT168_OSC / PLL_N) < 1000000U)
        return ERROR;

    // if ((LT168_OSC / PLL_N * PLL_M) > 400000000U || (LT168_OSC / PLL_N * PLL_M) < 200000000U)
    //     return ERROR;

    /* SYNCR */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(1U)); /* Unlock register */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(2U)); /* Unlock register */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(3U)); /* Unlock register */

    /* System clock won¡¯t be stopped and System clock source is from FXOSC(12MHz) until PLL locked */
    Bit_Set(CLOCK->SYNCR, CLOCK_SYNCR_PLLSRCEN_MASK);

    Bit_Clear(CLOCK->SYNCR, CLOCK_SYNCR_PLLEN_MASK); /* Disable PLL */

    /* PLLCSR */

    CLOCK->PLLCSR = (CLOCK->PLLCSR & ~CLOCK_PLLCSR_PLLCSRTEST_MASK) | (CLOCK_PLLCSR_PLLCSRTEST(1)); /* Unlock register */
    CLOCK->PLLCSR = (CLOCK->PLLCSR & ~CLOCK_PLLCSR_PLLCSRTEST_MASK) | (CLOCK_PLLCSR_PLLCSRTEST(2)); /* Unlock register */
    CLOCK->PLLCSR = (CLOCK->PLLCSR & ~CLOCK_PLLCSR_PLLCSRTEST_MASK) | (CLOCK_PLLCSR_PLLCSRTEST(3)); /* Unlock register */

    tempReg = CLOCK->PLLCSR;

    tempReg = CLOCK_PLLCSR_PLLM(PLL_M) | CLOCK_PLLCSR_PLLOD(PLL_OD) | CLOCK_PLLCSR_PLLN(PLL_N);

    CLOCK->PLLCSR = tempReg;

    Bit_Set(CLOCK->SYNCR, CLOCK_SYNCR_PLLEN_MASK);                      /* Enable PLL */
    for (; Bit_Read(CLOCK->PLLCSR, CLOCK_PLLCSR_PLLOCK_MASK) == Reset;) /* wait PLL lock */
    {
        asm("nop");
    }

    tempReg = CLOCK->SYNCR;

    Bit_Clear(tempReg, CLOCK_SYNCR_PLLDIV_MASK);

    tempReg |= CLOCK_SYNCR_PLLDIV(PLL_DIV);

    CLOCK->SYNCR = tempReg;

    asm("nop");
    asm("nop");
    asm("nop");

    Bit_Clear(CLOCK->PLLCSR, CLOCK_PLLCSR_PLLCSRTEST_MASK); /* Lock register */
    Bit_Clear(CLOCK->SYNCR, CLOCK_SYNCR_SYNCTEST_MASK);     /* Lock register */

    Get_SysClock();

    return OK;
}

/**
 * @brief PLL Initialize By CLOCK PLL Configuration Structure Pointer
 * @param {clock_pll_config_ts *} pll:Pointer to a clock pll configuration structure.
 * @return {ResultStatus}
 */
ResultStatus CLOCK_PLL_Init_flexible(clock_pll_config_ts *pll)
{
    uint32_t tempReg = 0U;

    /* Check pll parameter */
    if (pll->n > 15U || pll->n < 1U)
        return ERROR;
    if (pll->m > 16383U || pll->m < 4U)
        return ERROR;
    if (pll->od > 3U)
        return ERROR;
    if (pll->div > 63U || pll->div < 0U)
        return ERROR;

    if ((LT168_OSC / pll->n) > 50000000U || (LT168_OSC / pll->n) < 1000000U)
        return ERROR;

    if ((LT168_OSC / pll->n * pll->m) > 400000000U || (LT168_OSC / pll->n * pll->m) < 200000000U)
        return ERROR;

    /* SYNCR */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(1U)); /* Unlock register */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(2U)); /* Unlock register */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(3U)); /* Unlock register */

    /* System clock won¡¯t be stopped and System clock source is from FXOSC(12MHz) until PLL locked */
    Bit_Set(CLOCK->SYNCR, CLOCK_SYNCR_PLLSRCEN_MASK);

    Bit_Clear(CLOCK->SYNCR, CLOCK_SYNCR_PLLEN_MASK); /* Disable PLL */

    /* PLLCSR */

    CLOCK->PLLCSR = (CLOCK->PLLCSR & ~CLOCK_PLLCSR_PLLCSRTEST_MASK) | (CLOCK_PLLCSR_PLLCSRTEST(1U)); /* Unlock register */
    CLOCK->PLLCSR = (CLOCK->PLLCSR & ~CLOCK_PLLCSR_PLLCSRTEST_MASK) | (CLOCK_PLLCSR_PLLCSRTEST(2U)); /* Unlock register */
    CLOCK->PLLCSR = (CLOCK->PLLCSR & ~CLOCK_PLLCSR_PLLCSRTEST_MASK) | (CLOCK_PLLCSR_PLLCSRTEST(3U)); /* Unlock register */

    tempReg = CLOCK->PLLCSR;

    tempReg = CLOCK_PLLCSR_PLLM(pll->m) | CLOCK_PLLCSR_PLLOD(pll->od) | CLOCK_PLLCSR_PLLN(pll->n);

    CLOCK->PLLCSR = tempReg;

    Bit_Set(CLOCK->SYNCR, CLOCK_SYNCR_PLLEN_MASK);                      /* Enable PLL */
    for (; Bit_Read(CLOCK->PLLCSR, CLOCK_PLLCSR_PLLOCK_MASK) == Reset;) /* wait PLL lock */
    {
        asm("nop");
    }

    tempReg = CLOCK->SYNCR;

    Bit_Clear(tempReg, CLOCK_SYNCR_PLLDIV_MASK);

    tempReg |= CLOCK_SYNCR_PLLDIV(pll->div);

    CLOCK->SYNCR = tempReg;

    asm("nop");
    asm("nop");
    asm("nop");

    Bit_Clear(CLOCK->PLLCSR, CLOCK_PLLCSR_PLLCSRTEST_MASK); /* Lock register */
    Bit_Clear(CLOCK->SYNCR, CLOCK_SYNCR_SYNCTEST_MASK);     /* Lock register */

    Get_SysClock();

    return OK;
}

/**
 * @brief  ADC Clock Initialize
 * @param {clock_adc_clock_divider_te} div:CLOCK_ADC_DIV_0,CLOCK_ADC_DIV_1,
 *         ,...,CLOCK_ADC_DIV_14,CLOCK_ADC_DIV_15.
 * @param {FunctionState} state:where can be Enable,Disable.
 * @return {void}
 */
void CLOCK_ADC_CLOCK_Init(clock_adc_clock_divider_te div, FunctionState state)
{
    /* SYNCR */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(1U)); /* Unlock register */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(2U)); /* Unlock register */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(3U)); /* Unlock register */

    uint32_t tempReg = 0;

    tempReg = CLOCK->SYNCR;

    Bit_Clear(tempReg, CLOCK_SYNCR_ADCDIV_MASK);
    Bit_Clear(tempReg, CLOCK_SYNCR_ADCEN_MASK);

    Bit_Set(tempReg, CLOCK_SYNCR_ADCDIV(div) | CLOCK_SYNCR_ADCEN(state));

    CLOCK->SYNCR = tempReg;

    Bit_Clear(CLOCK->SYNCR, CLOCK_SYNCR_SYNCTEST_MASK); /* Lock register */
}

/**
 * @brief Chip Clock Output Pin Output Select
 * @param {clock_out_select_te} select:where can be CLOCK_Out_System_Clock,CLOCK_Out_128KHz_Clock.
 * @return {void}
 */
void CLOCK_Output_Select(clock_out_select_te select)
{
    /* SYNCR */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(1U)); /* Unlock register */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(2U)); /* Unlock register */
    CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(3U)); /* Unlock register */

    Bit_Clear(CLOCK->SYNCR, CLOCK_SYNCR_CLKOUTSEL_MASK);
    Bit_Set(CLOCK->SYNCR, CLOCK_SYNCR_CLKOUTSEL(select));

    Bit_Clear(CLOCK->SYNCR, CLOCK_SYNCR_SYNCTEST_MASK); /* Lock register */
}

/**
 * @brief Set Sleep Level
 * @param {clock_sleep_mode_te} mode:where can be CLOCK_Sleep_Mode_0,
 *          CLOCK_Sleep_Mode_1,CLOCK_Sleep_Mode_2,CLOCK_Sleep_Mode_3.
 * @return {ResultStatus} OK/ERROR.
 */
ResultStatus CLOCK_Sleep_Init(clock_sleep_mode_te mode)
{
    /* SYNCR */

    if (Bit_Read(CLOCK->SYNCR, CLOCK_SYNCR_ENLOWPOWER_MASK) == CLOCK_SYNCR_ENLOWPOWER_MASK) {
        CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(1U)); /* Unlock register */
        CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(2U)); /* Unlock register */
        CLOCK->SYNCR = (CLOCK->SYNCR & ~CLOCK_SYNCR_SYNCTEST_MASK) | (CLOCK_SYNCR_SYNCTEST(3U)); /* Unlock register */

        uint32_t tempReg = 0;
        tempReg          = CLOCK->SYNCR;
        tempReg |= 0x3C000089;

        Bit_Clear(tempReg, CLOCK_SYNCR_STBYMD_MASK);
        Bit_Set(tempReg, CLOCK_SYNCR_STBYMD(mode));

        CLOCK->SYNCR = tempReg;

        Bit_Clear(CLOCK->SYNCR, CLOCK_SYNCR_SYNCTEST_MASK); /* Lock register */
        return OK;
    } else {
        return ERROR;
    }
}

/**
 * @brief Set External Low Speed Oscillator Stable Time
 * @param {uint16_t} value:the value ranges from 0 to 65535.
 * @return {void}
 */
void CLOCK_Set_External_Low_Speed_Oscillator_Stable_Time(uint16_t value)
{
    CLOCK->LOSCCSR = (CLOCK->LOSCCSR & ~CLOCK_LOSCCSR_LOSCCSTEST_MASK) | (CLOCK_LOSCCSR_LOSCCSTEST(1U)); /* Unlock register */
    CLOCK->LOSCCSR = (CLOCK->LOSCCSR & ~CLOCK_LOSCCSR_LOSCCSTEST_MASK) | (CLOCK_LOSCCSR_LOSCCSTEST(2U)); /* Unlock register */
    CLOCK->LOSCCSR = (CLOCK->LOSCCSR & ~CLOCK_LOSCCSR_LOSCCSTEST_MASK) | (CLOCK_LOSCCSR_LOSCCSTEST(3U)); /* Unlock register */

    Bit_Clear(CLOCK->LOSCCSR, CLOCK_LOSCCSR_SXOSCST_MASK);
    Bit_Set(CLOCK->LOSCCSR, CLOCK_LOSCCSR_SXOSCST(value));

    Bit_Clear(CLOCK->LOSCCSR, CLOCK_LOSCCSR_LOSCCSTEST_MASK); /* Lock register */
}

/**
 * @brief  WatchDog Clock Source Select
 * @param {clock_watchdog_clock_source_te} source:where can be CLOCK_WatchDog_Source_128K,
 *          CLOCK_WatchDog_Source_32768.
 * @return {ResultStatus} OK/ERROR.
 */
ResultStatus CLOCK_WatchDog_Source_Select(clock_watchdog_clock_source_te source)
{
    uint16_t time = 0; /* Timing variable for timeout */

    CLOCK->LOSCCSR = (CLOCK->LOSCCSR & ~CLOCK_LOSCCSR_LOSCCSTEST_MASK) | (CLOCK_LOSCCSR_LOSCCSTEST(1U)); /* Unlock register */
    CLOCK->LOSCCSR = (CLOCK->LOSCCSR & ~CLOCK_LOSCCSR_LOSCCSTEST_MASK) | (CLOCK_LOSCCSR_LOSCCSTEST(2U)); /* Unlock register */
    CLOCK->LOSCCSR = (CLOCK->LOSCCSR & ~CLOCK_LOSCCSR_LOSCCSTEST_MASK) | (CLOCK_LOSCCSR_LOSCCSTEST(3U)); /* Unlock register */

    if (source == CLOCK_WatchDog_Source_128K) {
        for (; Bit_Read(CLOCK->LOSCCSR, CLOCK_LOSCCSR_SIRCRDY_MASK) == false;) /* wait Internal low speed oscillator (SIRC) ready */
        {
            time++;
            asm("nop");

            if (time == 0xFFFF) {
                Bit_Clear(CLOCK->LOSCCSR, CLOCK_LOSCCSR_LOSCCSTEST_MASK); /* Lock register */
                return ERROR;
            }
        }
        Bit_Clear(CLOCK->LOSCCSR, CLOCK_LOSCCSR_WDTCLKSEL_MASK); /* WDT Clock select 128Khz */
    } else {
        Bit_Set(CLOCK->LOSCCSR, CLOCK_LOSCCSR_SXOSCEN_MASK);                    /* SXOSC is enabled for WDT  */
        for (; Bit_Read(CLOCK->LOSCCSR, CLOCK_LOSCCSR_SXOSCRDY_MASK) == false;) /* External low speed oscillator (SXOSC) is ready */
        {
            time++;
            asm("nop");

            if (time == 0xFFFF) {
                Bit_Clear(CLOCK->LOSCCSR, CLOCK_LOSCCSR_LOSCCSTEST_MASK); /* Lock register */
                return ERROR;
            }
        }
        Bit_Set(CLOCK->LOSCCSR, CLOCK_LOSCCSR_WDTCLKSEL_MASK); /* WDT Clock select 32768 */
    }

    time = 0;
    for (; Bit_Read(CLOCK->LOSCCSR, CLOCK_LOSCCSR_WDTCLKCHGDONE_MASK) == false;) /* wait WDT clock switch done. */
    {
        time++;
        asm("nop");

        if (time == 0xFFFF) {
            Bit_Clear(CLOCK->LOSCCSR, CLOCK_LOSCCSR_LOSCCSTEST_MASK); /* Lock register */
            return ERROR;
        }
    }

    Bit_Clear(CLOCK->LOSCCSR, CLOCK_LOSCCSR_LOSCCSTEST_MASK); /* Lock register */
    return OK;
}

/**
 * @brief CLOCK Module Stop Control
 * @param {clock_module_stop_te} module:where can be CLOCK_Module_Stop_BLENDER,
 *        CLOCK_Module_Stop_COMP0,...,CLOCK_Module_Stop_RGB,CLOCK_Module_Stop_USBC.
 * @param {FunctionState} state:where can be Enable,Disable.
 * @return {void}
 */
void CLOCK_Module_Stop_Cmd(clock_module_stop_te module, FunctionState state)
{
    CLOCK->MSCR = (CLOCK->MSCR & ~CLOCK_MSCR_MSCRTEST_MASK) | (CLOCK_MSCR_MSCRTEST(1U)); /* Unlock register */
    CLOCK->MSCR = (CLOCK->MSCR & ~CLOCK_MSCR_MSCRTEST_MASK) | (CLOCK_MSCR_MSCRTEST(2U)); /* Unlock register */
    CLOCK->MSCR = (CLOCK->MSCR & ~CLOCK_MSCR_MSCRTEST_MASK) | (CLOCK_MSCR_MSCRTEST(3U)); /* Unlock register */

    Bit_Clear(CLOCK->MSCR, 1 << module);
    Bit_Set(CLOCK->MSCR, state << module);

    Bit_Clear(CLOCK->MSCR, CLOCK_MSCR_MSCRTEST_MASK); /* Lock register */
}

/**
 * @brief CLOCK Measurement,could measure internal low speed oscillator(128KHz) and pll output frequency
 * @param {clock_measurement_source_te} source: where can be CLOCK_Measurement_128K,CLOCK_Measurement_PLL.
 * @return {float} the measuring result.
 */
float CLOCK_Measurement(clock_measurement_source_te source)
{
    float count_clock_value = 0;
    if (source == CLOCK_Measurement_128K) {
        CLOCK->OBTCR = 0x00001200; /* reset OBTCR */

        Bit_Clear(CLOCK->OBTCR, CLOCK_OBTCR_BIST_RESETN_MASK); /* clear BIST_RESETN */

        CLOCK->OBTCR1 = CLOCK_OBTCR1_BIST_TARGET(0xFFFF) | CLOCK_OBTCR1_BIST_HOLD_TARGET(0xFFFF); /* set BIST_TARGET */

        Bit_Set(CLOCK->OBTCR, CLOCK_OBTCR_BIST_MODE_MASK); /* set BIST_MODE bit*/

        Bit_Clear(CLOCK->OBTCR, CLOCK_OBTCR_BIST_IRC_SEL_MASK); /* count 128KHz */

        Bit_Set(CLOCK->OBTCR, CLOCK_OBTCR_BIST_START_MASK); /* set BIST_START */

        Bit_Set(CLOCK->OBTCR, CLOCK_OBTCR_BIST_RESETN_MASK); /* set BIST_RESETN */

        while (Bit_Read(CLOCK->OBTRR, CLOCK_OBTRR_BIST_DONE_MASK) == 0) asm("nop");

        count_clock_value = 1.0 * LT168_OSC * (CLOCK->OBTCNTR >> 16) / 0xFFFF / 1000;
    } else {
        CLOCK->OBTCR = 0x00001200; /* reset OBTCR */

        Bit_Clear(CLOCK->OBTCR, CLOCK_OBTCR_BIST_RESETN_MASK); /* clear BIST_RESETN */

        CLOCK->OBTCR1 = CLOCK_OBTCR1_BIST_TARGET(196) | CLOCK_OBTCR1_BIST_HOLD_TARGET(16); /* set BIST_TARGET */

        Bit_Set(CLOCK->OBTCR, CLOCK_OBTCR_BIST_MODE_MASK); /* set BIST_MODE bit*/

        Bit_Set(CLOCK->OBTCR, CLOCK_OBTCR_BIST_IRC_SEL_MASK); /* count PLL */

        Bit_Set(CLOCK->OBTCR, CLOCK_OBTCR_BIST_START_MASK); /* set BIST_START */

        Bit_Set(CLOCK->OBTCR, CLOCK_OBTCR_BIST_RESETN_MASK); /* set BIST_RESETN */

        while (Bit_Read(CLOCK->OBTRR, CLOCK_OBTRR_BIST_DONE_MASK) == 0) asm("nop");

        count_clock_value = 1.0 * LT168_OSC * (CLOCK->OBTCNTR >> 16) / 196 / (1000000) * 2;
    }
    return count_clock_value;
}

/*!<---------------End of Code--------------->!*/


